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a
FEATURES Analog Input Block 11-Bit Resolution Analog-to-Digital (A/D) Converter 7 Single-Ended (SE) Analog Inputs 4 Simultaneously Sampled Analog Inputs Expansion with 4 Multiplexed Inputs 3.2 s Conversion Time/Channel 0 V-5 V Analog Input Range Internal 2.5 V Reference PWM Synchronized Sampling Capability 12-Bit PWM Timer Block Three-Phase Center-Based PWM 1.5 kHz-25 kHz PWM Switching Frequency Range Programmable Deadtime Programmable Pulse Deletion PWM Synchronized Output External PWM Shutdown Vector Transformation Block 12-Bit Vector Transformations Forward and Reverse Clarke Transformations Forward and Reverse Park Rotations 2.9 s Transformation Time Programmable Digital I/O Port 6-Bit Configurable Digital I/O Change of State Interrupt Support DSP & Microcontroller Interface 12 Bit Memory Mapped Registers Twos Complement Data Format 6.25 MHz to 25 MHz Operating Clock Range 68-Pin PLCC Package Single 5 V DC Power Supply Industrial Temperature Range GENERAL DESCRIPTION
RESET WR A0-3 RD CS IRQ CLK REFOUT REFIN CONVST U V W AUX AUX0 AUX1 AUX2 AUX3 PWMSYNC A AP B BP C CP STOP
Motion Coprocessor ADMC201
FUNCTIONAL BLOCK DIAGRAM
D0-D11 EMBEDDED CONTROL SEQUENCER DATABUS CONTROL BUS
INTERNAL REFERENCE
CONTROL REGISTERS
11-BIT A/D CONVERTER VECTOR TRANSFORMATION BLOCK MULTIPLEXER EXPANSION BLOCK PROG. DIGITAL I/O PORT 12-BIT PWM TIMER BLOCK
PIO 0-5
Flexible Analog Channel Sequencing
The ADMC201 supports acquisition of 2, 3, or 4 channels per group. Converted channel results are stored in registers and the data can be read in any order. The sampling and conversion time for two channels is 8 s, three channels is 11.2 s, and four channels is 14.4 s (using a 12.5 MHz system clock).
Embedded Control Sequencer
The ADMC201 is a motion coprocessor that can be used with either microcontrollers or digital signal processors (DSP). It provides the functionality that is required to implement a digital control system. In a typical application, the DSP or microcontroller performs the control algorithms (position, speed, torque and flux loops) and the ADMC201 provides the necessary motor control functions: analog current data acquisition, vector transformation, digital inputs/outputs, and PWM drive signals.
PRODUCT HIGHLIGHTS Simultaneous Sampling of Four Inputs
The embedded control sequencer off-loads the DSP or microprocessor, reducing the instructions required to read analog input channels, control PWM timers and perform vector transformations. This frees the host processor for performing control algorithms.
Fast DSP/Microprocessor Interface
The high speed digital interface allows direct connection to 16-bit digital signal processors and microprocessors. The ADMC201 has 12 bit memory mapped registers with twos complement data format and can be mapped directly into the data memory map of a DSP. This allows for a single instruction read and write interface.
Integration
A four channel sample and hold amplifier allows three-phase motor currents to be sampled simultaneously, reducing errors from phase coherency. Sample and hold acquisition time is 1.6 s and conversion time per channel is 3.2 s (using a 12.5 MHz system clock). REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
The ADMC201 integrates a four channel simultaneous sampling analog-to-digital converter, four channel analog multiplexer, analog reference, vector transformation, six digital inputs/outputs, and three-phase PWM timers into a 68-pin PLCC. Integration reduces cost, board space, power consumption, and design and test time.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
ADMC201-SPECIFICATIONS T = -40 C to +85 C unless otherwise noted)
A
(VDD = +5 V
Units
5%; AGND = DGND = 0 V; REFIN = 2.5 V; External Clock = 12.5 MHz;
Conditions/Comments
Twos Complement Data Format Integral Nonlinearity Any Channel Between Channels Any Channel Between Channels fIN = 600 Hz Sine Wave, fSAMPLE = 55 kHz, 600 Hz Sine Wave Applied to Unselected Channels
Parameter
ANALOG-TO-DIGITAL CONVERTER Resolution Relative Accuracy Differential Nonlinearity Bias Offset Error Bias Offset Match Full-Scale Error Full-Scale Error Match Conversion Time/Channel Signal-to-Noise Ratio (SNR)2 Channel-to-Channel Isolation Two-/Three-Phase Mode Three-/Three-Phase Mode ANALOG INPUTS Input Voltage Level Analog Input Current Input Capacitance TRACK AND HOLD Aperture Delay Aperture Time Delay Match SHA Acquisition Time Droop Rate REFERENCE INPUT Voltage Level Reference Input Current REFERENCE OUTPUT Voltage Level Voltage Level Tolerance Drive Capability LOGIC VIL VIH VOL VOH Input Leakage Current Three-State Leakage Current Input Capacitance 12-BIT PWM TIMERS Resolution Programmable Deadtime Range Programmable Deadtime Increments Programmable Pulse Deletion Range Programmable Deletion Increments Minimum PWM Frequency
1
ADMC201AP
11 2 2 5 4 6 4 40 60 -58 -55 0-5 100 10 200 20 20 5 2.5 50 2.5 5 200 0.8 2.0 0.4 4.5 1 1 20 12 0-10.08 2 0-10.16 1 1.5
Bits LSB max LSB max LSB max LSB max LSB max LSB max System CLK Cycles dB min dB max dB max Volts A max pF typ ns max ns max System CLK Cycles mV/ms max V dc A max Volts % max A max V max V min V max V min A max A max pF typ Bits s System CLK Cycles s System CLK Cycle kHz
Any Channel Between Channels
Full Load
ISINK = 400 A, VDD = 5 V ISOURCE = 20 A, VDD = 5 V
160 ns 80 ns Resolution Varies with PWM Switching Frequency (10 MHz Clock: 20 kHz = 9 Bits, 10 kHz = 10 Bits, 5 kHz = 11 Bits, 2.5 kHz = 12 Bits). Higher Frequencies are Available with Lower Resolution Park & Clarke Transformation
VECTOR TRANSFORMATION Radius Error Angular Error Reverse Transformation Time Forward Transformation Time EXTERNAL CLOCK INPUT Range INTERNAL SYSTEM CLOCK Range POWER SUPPLY CURRENT IDD
NOTES 1 Measurements made with external reference. 2 Tested with PWM Switching Frequency of 25 kHz. Specifications subject to change without notice.
0.7 30 37 40 6.25-25
% max arc min max System CLK Cycles System CLK Cycles MHz If > 12.5 MHz, Then It Is Necessary to Divide Down via SYSCTRL Register
6.25-12.5 20
MHz mA max
-2-
REV. B
ADMC201
Table I. Timing Specifications (VDD = 5 V,
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol tperclk tpwhclk tpwlclk tsucsb_wrb tsuaddr_wrb tsudata_wrb thdwrb_data thdwrb_addr thdwrb_csb tpwlwrb1 tpwhwrb1 thdwrb_clk_h1 tsuwrb_clk_h1 tsuwrb_clk_l1 thdclk_wrb_l1 tsucsb_rdb tsuaddr_rdb thdrdb_addr thdrdb_csb tpwlrdb tpwhrdb tsurdb_clk_h thdrdb_clk_h tpwlresetb Timing Requirements CLK Period CLK Pulsewidth, High CLK Pulsewidth, Low CS Low before Falling Edge of WR ADDR Valid before Falling Edge of WR DATA Valid before Rising Edge of WR DATA Hold after Rising Edge of WR ADDR Hold after Rising Edge of WR CS Hold after Rising Edge of WR WR Pulsewidth, Low WR Pulsewidth, High WR Low after Rising Edge of CLK WR High before Rising Edge of CLK WR High before Falling Edge of CLK WR High after Falling Edge of CLK CS Low before Falling Edge of RD ADDR Valid before Falling Edge of RD ADDR Hold after Rising Edge of RD CS Hold after Rising Edge of RD RD Pulsewidth, Low RD Pulsewidth, High RD Low before Rising Edge of CLK RD Low after Rising Edge of CLK RESET Pulsewidth, Low
5%; TA = -40 C to +85 C)
Min 40 20 20 0 0 13 4.5 4.5 4.5 20 20 7 7 10 10 0 0 0 0 20 20 7.5 7.5 2 x tperclk Max 160 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
9
NOTE 1 All WRITES to the ADMC201 must occur within 1 System Clock Cycle (0 wait states).
Number 25 26 27 28
Symbol tdlyrdb_data thdrdb_data tpwh_pio tpwl_pio
Switching Characteristics DATA Valid after Falling Edge of RD DATA Hold after Rising Edge of RD Digital I/O Pulsewidth, High Digital I/O Pulsewidth, Low
Min 0 2 x tperclk 2 x tperclk
Max 23
Units ns ns ns ns
1 2 CLK 3
CLK 12 CS 15 13 9 8 A0-A3 11 14
Figure 1. Clock Input Timing
CLK 24 RESET
WR
10
DATA
Figure 2. Reset Input Timing
4 6 7 NOTE: ALL WRITES TO THE ADMC201 MUST OCCUR WITHIN ONE SYSTEM CLOCK CYCLE (i.e., 0 WAIT STATES) 5
Figure 3. Write Cycle Timing Diagram
REV. B
-3-
ADMC201
CLK 23 CS 22
A0-A3 20 RD 26 DATA 25 16 17 18 19 21
Figure 4. Read Cycle Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
ORDERING GUIDE
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . -0.3 V to +7.0 V Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD Analog Reference Input Voltage . . . . . . . . . . . . -0.3 V to VDD Digital Output Voltage Swing . . . . . . . . . . . . . . -0.3 V to VDD Analog Reference Output Swing . . . . . . . . . . . . -0.3 V to VDD Operating Temperature . . . . . . . . . . . . . . . . . -40C to +85C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +280C
*Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Part Number ADMC201AP
Temperature Range -40C to +85C
Package Description 68-Pin PLCC
Package Option P-68A
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADMC201 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. B
ADMC201
PIN DESIGNATIONS
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
Mnemonic Type
D9 D10 D11 PIO0 PIO1 PIO2 PIO3 PIO4 PIO5 VDD A3 A2 A1 A0 NC RESET CONVST IRQ VDD DGND CLK WR RD CS NC VDD AGND AGND U V W SGND REFIN AUX3 AUX2 AUX1 AUX0 BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR SUP I/P I/P I/P I/P I/P I/P O/P SUP GND I/P I/P I/P I/P SUP GND GND I/P I/P I/P GND I/P I/P I/P I/P I/P
Description
Data Bit 9 Data Bit 10 Data Bit 11, MSB Programmable Digital I/O Bit 0 Programmable Digital I/O Bit 1 Programmable Digital I/O Bit 2 Programmable Digital I/O Bit 3 Programmable Digital I/O Bit 4 Programmable Digital I/O Bit 5 +5 V Digital Power Supply Address Bit 3, MSB Address Bit 2 Address Bit 1 Address Bit 0, LSB No Connect Chip Reset A/D Conversion Start Interrupt Request (Pull-Up Required) +5 V Digital Power Supply Digital Ground External Clock Input Write Select Output Enable/Read Chip Select No Connect +5 V Analog Power Supply Analog Ground Analog Ground Analog Input U Analog Input V Analog Input W Analog Signal Ground Analog Reference Input Auxiliary Analog Input 3 Auxiliary Analog Input 2 Auxiliary Analog Input 1 Auxiliary Analog Input 0
Pin
38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
Mnemonic Type
REFOUT VDD DGND DGND DGND DGND VDD NC DGND STOP PWMSYNC CP C BP NC B AP A DGND DGND DGND VDD D0 D1 D2 D3 D4 D5 D6 D7 D8 O/P SUP GND GND GND GND SUP GND I/P O/P O/P O/P O/P O/P O/P O/P GND GND GND SUP BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR
Description
Internal 2.5 V Analog Reference +5 V Digital Power Supply Digital Ground Digital Ground Digital Ground Digital Ground +5 V Digital Power Supply No Connect Digital Ground PWM Timer Output Disable PWM Synchronization Output PWM Timer Output C Prime PWM Timer Output C PWM Timer Output B Prime No Connect PWM Timer Output B PWM Timer Output A Prime PWM Timer Output A Digital Ground Digital Ground Digital Ground +5 V Digital Power Supply Data Bit 0, LSB Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Data Bit 8
Pin Types I/P = Input Pin O/P = Output Pin GND = Ground Pin
Pin Types BIDIR = Bidirectional Pin SUP = Supply Pin
PIN CONFIGURATION
PIO3 PIO2 PIO5 PIO4 PIO1 PIO0 D11 D10 D5 D9 D7 D6 D4 D2 D8 D3 D1
60 D0 59 V DD 58 DGND 57 DGND 56 DGND 55 A 54 AP 53 B 52 NC 51 BP 50 C 49 CP 48 PWMSYNC 47 STOP 46 DGND 45 NC 44 VDD 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61 PIN 1 IDENTIFIER
VDD 10 A3 11 A2 12 A1 13 A0 14 NC 15 RESET 16 CONVST 17 IRQ 18 VDD 19 DGND 20 CLK 21 WR 22 RD 23 CS 24 NC 25 VDD 26
ADMC201
TOP VIEW (Not to Scale)
AUX2
AUX3
AUX1
AUX0
U
AGND
AGND
DGND
DGND
SGND
DGND
NC = NO CONNECT
REV. B
-5-
REFOUT VDD
REFIN
DGND
V W
ADMC201
ANALOG INPUT BLOCK Interrupt Driven Method
The ADMC201 contains an 11-bit resolution, successive approximation analog-to-digital (A/D) converter with twos complement output data format. The analog input range is 2.5 V (0 V-5 V) with a 2.5 V offset as defined by REFIN. The on-chip 2.5 V 5% reference is utilized by connecting the REFOUT pin to the REFIN pin. The input stage to the A/D converter is a four channel SHA which allows the four channels (U, V, W and AUX) to be held simultaneously and then sequentially digitized. The auxiliary input (AUX) is fed by a four channel multiplexer that allows the channels AUX0, AUX1, AUX2 and AUX3 to be individually converted along with the primary channels U, V and W. The auxiliary inputs are ideal for reading slower changing variables such as bus voltage and temperature. The A/D conversion time is determined by the system clock frequency, which can range from 6.25 MHz to 12.5 MHz. The Sample and Hold (SHA) acquisition time is 20 system clock cycles and is independent of the number of channels sampled and/or digitized. Forty system clock cycles are required to complete each A/D conversion. The analog channel sampling is flexible and is programmable through the SYSCTRL register. The minimum number of channels per conversion is two. The throughput time of the analog acquisition block can be calculated as follows:
Interrupts can be used to indicate the end of conversion for a group of channels. Before beginning any A/D conversions, Bit 7 of the SYSCTRL register must be set to 1 to enable A/D conversion interrupts. Then, when an A/D conversion is complete, an interrupt will be generated. After an interrupt is detected, Bit 0 of the SYSSTAT register must be checked to determine if the A/D converter was the source. Reading the SYSSTAT register automatically clears the interrupt flag bits.
Software Timing Method
An alternative method is to use the DSP or microcontroller to keep track of the amount of time elapsed between CONVST and the expected completion time (n x tCONV).
Reading Results
The 11-bit A/D conversion results for channels U, V, W and AUX are stored in the ADCU, ADCV, ADCW and ADCAUX registers respectively. The twos complement data is left justified and the LSB is set to zero. The relationship between input voltage and output coding is shown in Figure 5.
OUTPUT CODE FULL-SCALE TRANSITION
01 1 1 1 1 1 1 1 1 1 0
t AA = t SHA + (n x tCONV )
where tAA = analog acquisition time, n = # channels, tSHA = SHA acquisition time (20 x system clock period), tCONV = conversion time (40 x system clock period) per channel. A/D Conversions are initiated via the CONVST pin. A synchronizing pulse (PWMSYNC) is provided at the beginning of each PWM cycle. This pulse can be used to synchronize the A/D conversion process to the PWM switching frequency.
Operating the A/D Converter
FS = 5V 000000000000 LSB = 5V 2048
100000000000 0V 5V-1LSB 2.5 INPUT VOLTAGE
Figure 5. Transfer Function
Sample and Hold
The A/D converter can be set up to convert a sequence of channels as defined in the SYSCTRL register (see Table VI). The default channel select mode after RESET is to convert channels V and W only. This is two-/three-phase mode. Three-/three-phase mode converts channels U, V, W, and/or AUX. Three-/threephase mode is selected by writing a 1 to Bit 3 of the SYSCTRL register. After the conversion process is complete, the channels can be read in any order. There are two methods that can be used to indicate when the A/D conversions are completed and the data is ready: interrupt driven and software timing.
After powering up the ADMC201, bring the RESET pin low for a minimum of two clock cycles in order to enable A/D conversions. Before initiating the first conversion (CONVST) after a reset, the SHA time of 20 system clock cycles must occur. A conversion is initiated by bringing CONVST high for a minimum of one system clock cycle. The SHA goes into hold mode at the falling edge of clock. Following completion of the A/D conversion process, a minimum of 20 system clock cycles are required before initiating another conversion in order to allow the sample and hold circuitry to reacquire the input signals. If a CONVST is initiated before the 20 clock cycles have elapsed, the embedded control sequencer will delay conversion until this requirement is met.
-6-
REV. B
ADMC201
PWM TIMER BLOCK OVERVIEW Programmable Deadtime
The PWM timers have 12-bit resolution and support programmable pulse deletion and deadtime. The ADMC201 generates three center-based signals A, B and C based upon user-supplied duty cycles values. The three signals are then complemented and adjusted for programmable deadtime to produce the six outputs. The ADMC201 PWM master switching frequency can range from 2.5 kHz to 20 kHz, when using a 10 MHz system clock. The master frequency selection is set as a fraction of the PWMTM register. If the system clock is 10 MHz, then the minimum edge resolution available is 100 ns. The output format of the PWM block is active LO. There is an external input to the PWM timers (STOP) that will disable all six outputs within one system clock when the input is HIGH. The ADMC201 has a PWM Synchronization output (PWMSYNC) which brings out the master switching frequency from the PWM timers. The width of the PWMSYNC pulse is equal to one system clock cycle. For example, if the system clock is 10 MHz, the PWMSYNC width would be equal to 100 ns.
PWM Master Switching Period Selection
With perfectly complemented PWM drive signals and nonideal switching characteristics of the power devices, both transistors in a particular leg might be switched on at the same time, resulting in either a power supply trip, inverter trip or device destruction. In order to prevent this, a delay must be introduced between the complemented signal edges. For example, the rising edge of AP occurs before the falling edge of A, and the falling edge of the complemented A occurs after the rising edge of A. This capability is known as programmable deadtime. The ADMC201 programmable deadtime value is loaded into the 7-bit PWMDT register, in which the LSB is set to zero internally, which means the deadtime value is always divisible by two. With a 10 MHz system clock, the 0-126 range of values in PWMDT yield a range of deadtime values from 0 s to 12.6 s in 200 ns steps. Figure 6 shows PWM timer A with a programmable deadtime of PWMDT.
PWMTM
The switching time is set by the PWMTM register which should be loaded with a value equal to the system clock frequency divided by the desired master switching frequency. For example, if the desired switching frequency is 8 kHz and the system clock frequency is 10 MHz, then the PWMTM register should be loaded with 1250 (10 MHz/8 kHz). The PWMCHA, PWMCHB and PWMCHC registers are loaded with the desired on-time and their values would be calculated as a ratio of the PWMTM register value. Note: Desired Pulse Density = (PWMCHx register)/( PWMTM register). The beginning of each PWM cycle is marked by the PWMSYNC signal. New values of PWMCHA, PWMCHB and PWMCHC must all be loaded into their respective registers at least four system clock cycles before the beginning of a new PWM cycle. All three registers must be updated for any of them to take effect. New PWM on/off times are calculated during these four clock cycles and therefore the PWMCHA, PWMCHB and PWMCHC registers must be loaded before this time. If this timing requirement is not met, then the PWM outputs may be invalid during the next PWM cycle.
PWM Example
PWMCHA - PWMDT A
AP PWMCHA + PWMDT
Figure 6. Programmable Deadtime Example
Pulse Deletion
The following example uses a system clock speed of 10 MHz. The desired PWM master switching frequency is 8 kHz and the desired on-time for the timers A, B and C are 25%, 50% and 10% respectively. The values for the PWMCHA, PWMCHB and PWMCHC registers must be calculated as ratios of the PWMTM register (1250 in this example). To achieve these duty cycles, load the PWMCHA register with 313 (1250 x 0.25), PWMCHB with 625 (1250 x 0.5) and PWMCHC with 125 (1250 x 0.1).
The pulse deletion feature prevents a pulse from being generated when the user-specified duty cycle results in a pulse duration shorter than the user-specified deletion value. The pulse deletion value is loaded into the 7-bit register PWMPD. When the user-specified on-time for a channel would result in a calculated pulse width less than the value specified in the PWMPD register, then the PWM outputs for that channel would be set to full off (0%) and its prime to full on (100%). This is valid for A, AP, B, BP, C and CP. This feature would be used in an environment where the inverter's power transistors have a minimum switching time. If the user-specified duty cycle would result in a pulse duration shorter than the minimum switching time of the transistors, then pulse deletion should be used to prevent this occurrence. With a 10 MHz system clock, the 0-127 range of values in PWMPD yield a range of deadtime values from 0 s to 12.7 s in 100 ns steps.
External PWM Shutdown
There is an external input pin (STOP) to the PWM timers that will disable all six outputs when it goes HIGH. When the STOP pin goes HIGH, the PWM timer outputs will all go HIGH within one system clock cycle. When the STOP pin goes LOW, the PWM timer outputs are re-enabled within one system clock cycle. If external PWM shutdown isn't required, tie the STOP pin LOW.
REV. B
-7-
ADMC201
VECTOR TRANSFORMATION BLOCK OVERVIEW
The Vector Transformation Block performs both Park and Clarke coordinate transformations to control a three-phase motor (Permanent Magnet Synchronous Motor or Induction Motor) via independent control of the decoupled rotor torque and flux currents. The Park & Clarke transformations combine to convert three-phase stator current signals into two orthogonal rotor referenced current signals Id and Iq. Id represents the flux or magnetic field current and Iq represents the torque generating current. The Id and Iq current signals are used by the processor's motor torque control algorithm to calculate the required direct Vd and quadrature Vq voltage components for the motor. The forward Park and Clarke transformations are used to convert the Vd and Vq voltage signals in the rotor reference frame to three-phase voltage signals (U, V, W) in the stator reference frame. These are then scaled by the processor and written to the ADMC201's PWM registers in order to drive the inverter. The figures below illustrate the Clarke and Park Transformations respectively.
Iw
120
Vy
W
120
120
U
120
V Vx
Equivalent Two-Phase Voltage
Three-Phase Stator Voltage
Figure 10. Forward Clarke Transformation
Operating/Using the Vector Transformation Block
After powering up the ADMC201, RESET must be driven low for a minimum of two clock cycles to enable vector transformations. The vector transformation block can perform either a forward or reverse transformation. Reverse Transformation is defined by the following operations: (a) Clarke: 3-phase current signals to 2-phase current signals followed by (b) Park: 2-phase current signals cross multiplied by sin , cos which effectively measures the current components with respect to the rotor (stationary) where is the electrical angle of the rotor field with respect to the stator windings.
Iy
120
Iu
120
Iv Ix
Three-Phase Stator Currents
Equivalent Two-Phase Currents
Forward transformation is defined by the following operations: (a) Park: 2-phase voltage signals cross multiplied by sin , cos followed by (b) Clarke: 2-phase to 3-phase voltage signal conversion. In order to provide maximum flexibility in the target system, the ADMC201 operates in an asynchronous manner. This means that the functional blocks (analog input, reverse transformation, forward transformation and PWM timers) operate independently of each other. The reverse and forward vector transformation operations cannot occur simultaneously. All vector transformation registers, except for RHO/RHOP, are twos complement. RHO/RHOP are unsigned ratios of 360. For example, 45 would be 45/360 x 212.
Performing a Reverse Transformation
Figure 7. Reverse Clarke Transformation
Iy
Iq
90
ROTOR REFERENCE FRAME AXIS
Ix
Id
Rotating Reference Frame
Stationary Reference Frame
Figure 8. Reverse Park Transformation
Vq
A reverse transformation is initiated by writing to the reverse rotation angle register RHO and operates on the values in the PHIP1, PHIP2 and PHIP3 registers. When the reverse transformation is in 2/3 mode, PHIP1 is calculated from PHIP2 and PHIP3. This is used in systems where only two-phase currents are measured. The reverse transformation 2/3 mode is set by clearing Bit 10 in the SYSCTRL register and is the default mode after RESET. In order to perform a reverse transformation, first write to the PHIP2 and PHIP3 registers, and to the PHIP1 register if not in 2/3 mode. Then initiate the transformation by writing the reverse rotation angle to the RHO register. The reverse rotation will be completed in 37 system clock cycles after the rotation is initiated. If Bit 6 of the system control register is set, then an interrupt will be generated on completion. When an interrupt occurs, the user must check Bit 1 of the SYSSTAT register to determine if the vector transformation block was the source of the interrupt. During the vector transformation, the vector transformation registers must not be written to or the vector rotation results will be invalid.
-8-
Vy
90
Vd
Vx
Stationary Reference Frame
Rotating Reference Frame
Figure 9. Forward Park Transformation
REV. B
ADMC201
Reverse Clarke Transformation Forward Park Rotation
The first operation is the Clarke transformation in which the three-phase motor current signals (Iu, Iv, Iw) are converted to sine and cosine orthogonal signals (Ix and Iy). These signals represent the equivalent currents in a two-phase ac machine and is the signal format required for the Park rotation. The threephase input signals are of the form: PHIP1 Iu = Is cos PHIP2 Iv = Is cos ( + 120) PHIP3 Iw = Is cos ( + 240) and the Park rotation requires inputs in the form Is cos and Is sin , therefore we need to generate Is sin . This is calculated from: IY Is sin = 1 (Is cos ( + 240) - Is cos ( +120))
3
If the input signals are represented by Vd and Vq, then the transformation can be described by: VX VY Vx = Vd x cos - Vq x sin Vy = Vd x sin + Vq x cos
where Vx and Vy are the outputs of the Park Rotation, and are the inputs to the reverse Clarke transformation.
Forward Clarke Transformation (2- to 3-Phase)
The second operation to be applied to the above results, is the Forward Clarke Transformation where 2-phase (stator) voltage signals are converted to 3-phase (stator) voltage signals. For the inverse Clarke transform we require three-phase outputs of the form below: PHV1 PHV2 PHV3 V cos V cos ( + 120) V cos ( + 240)
After the reverse transform, registers Ix and Iy contain the 2phase input current information. In the case where 2- of 3-phase information (PHIP2/3 only) is provided, then PHIP1 will be derived from the simple fact that all sum to zero. This value is then placed in the IX register. IX = Ix = Is cos = - Is cos ( + 120) - Is cos ( + 240)
Reverse Park Rotation
We have two quadrature voltages (V cos and V sin ) available. PHV2 PHV3 V cos ( + 120) = - V cos ( + 240) = -
1 x V cos - 3 x V sin 2 2 1 x V cos + 3 x V sin 2 2
IX/IY are then processed together with the digital angle (RHO) by a Park rotation. If the input signals are Ix and Iy, then the rotation can be described by: ID IQ Id = Ix x cos + Iy x sin Iq = -Iy x sin + Iy x cos
PROGRAMMABLE DIGITAL INPUT/OUTPUT PORT
The ADMC201 has a six bit programmable digital I/O port. Each bit is individually configurable as input or output. All bits configured as inputs have the ability to operate as interrupt sources. Each pin is independently capable of generating an interrupt should its input level change.
Configuring the Programmable Digital I/O Port
where ID and IQ are the outputs of the Park rotation. Cos and sin are required for the Park rotation, and are calculated internally. Substituting for Ix and Iy in the above yields: ID IQ Id = Is cos x cos + Is sin x sin = Is cos ( - ) Iq = Is sin x cos - Is cos x sin = Is sin ( - )
Performing a Forward Transformation
In order to perform a forward rotation, write values to the VD and VQ registers and then initiate the transformation by writing the rotation angle to the register RHOP. The forward transformation will only operate correctly when Bit 10 in the SYSCTRL register is set (i.e., in 3/3 mode). The forward rotation will be completed in 40 system clock cycles after the rotation is initiated. If Bit 6 of the system control register is set, then an interrupt will be generated on completion. When an interrupt occurs, the user must check Bit 1 of the system status register, SYSSTAT, to determine if the vector transformation block was the source of the interrupt. During the vector transformation, the transformation registers must not be written to or the vector rotation results will be invalid.
The PIOCTRL register is used to configure the individual bits on the programmable digital I/O port as either inputs or outputs and to enable change of state interrupts. The lower six bits of PIOCTRL control the direction (either input or output) of the individual bits. A zero configures the corresponding bit as an input; conversely a 1 configures the corresponding bit as an output. The upper six bits of PIOCTRL are used to enable the individual bits for use as change of state interrupt sources. A 0 disables change of state interrupt generation and a 1 enables change of state interrupt generation. The interrupt enable for a bit configured as an output is ignored. At power-up or RESET, all six bits of the digital port are configured as input and change of state interrupt generation is disabled.
Using the Programmable Digital I/O Port
The PIODATA register is used to write to and read from the digital I/O port. Bits 0-5 of the PIODATA register correspond to PIO 0-5 on the ADMC201. Bits 6-11 of PIODATA are unused and always contain 0. Read from PIODATA to determine the state of PIO 0-5. Write to PIODATA to change the states of PIO 0-5. Writing to bits configured as input has no effect. Reading from bits configured as output will return the last value written.
REV. B
-9-
ADMC201
INTERRUPT GENERATION POWER SUPPLY CONNECTIONS AND SETUP
There are three interrupt sources on the ADMC201 that may be independently enabled to generate interrupts. The first interrupt source is the Analog Input Block, which, if enabled, generates an interrupt at the end of conversion. The second interrupt source is the Vector Transformation Block, which, if enabled, generates an interrupt at the end of a Vector Transformation. The third interrupt source is the Digital I/O Block. Each digital I/O bit, if configured for input and enabled, generates an interrupt when its input level changes. When a 1 is stored in Bit 7 of the SYSCTRL register, ADC interrupts are enabled. When a 1 is stored in Bit 6 of the SYSCTRL register, Vector Transformation interrupts are enabled. When a 1 is stored in any of Bits 6-11 of the PIOCTRL register, digital I/O change of state interrupts are enabled for Bits 0-5 respectively. Upon a reset of the chip, all bits are set to the default condition, 0, thus disabling all interrupts. When an enabled interrupt occurs, Bit 11 of the SYSSTAT register becomes a 1. If that interrupt had been an ADC interrupt, Bit 0 of SYSSTAT register would also be set to 1. If that interrupt had been a Vector Transformation interrupt, Bit 1 of SYSSTAT would be set to 1. If that interrupt had been a digital I/O interrupt, then Bit 2 of the SYSSTAT would be set to 1. Whenever the SYSSTAT register is read, these four bits go back to their default state, 0, immediately after their values are loaded onto the data bus. Upon a reset, these four bits also go to their default state, 0. The IRQ pin has an open-drain driver, which will drive it low at the appropriate times, but the user must supply an external pullup resistor to bring the node back high when it is not being pulled low. The IRQ pin operates in one of two modes, edge mode or level mode. In edge mode, when an enabled interrupt occurs, the IRQ pin will be driven low for one system clock period. In level mode, when an enable interrupt occurs, the IRQ pin will be driven low, and will remain low until the SYSSTAT register is read. The combination of level mode and the open-drain driver allows multiple interrupt sources in an application to drive a single interrupt input line on the host DSP or microprocessor. Edge mode or level mode is determined with Bit 8 of the SYSCTRL register. Edge mode (0) is the default; a 1 in this bit will put the IRQ pin into level mode. The recommended method of using the interrupt generation capability is to set edge or level mode, enable the appropriate interrupts, and then monitor the IRQ line. After the IRQ pin goes low, the SYSSTAT register of the ADMC201 should be read, (1) to determine if it was this chip that caused the interrupt, if other lines are wired together with this IRQ pin, and (2) if it was this chip, to determine if it was generated by the Analog Input, Digital I/O and/or the Vector Transformation Blocks. Once this is done, the appropriate interrupt handling routine may be executed.
APPLICATION NOTE LIST
The nominal positive power supply level (VDD) is +5 V 5%. The Positive Power supply VDD should be connected to all ADMC201 VDD pins (10, 19, 26, 39, 44, 59). The SGND pin (32) and both AGND pins (27, 28) should be star point connected at a point close to the AGND pins of the ADMC201. The DGND pins (20, 40, 41, 42, 43, 46, 56, 57, 58) should also be connected to AGND pins close to the ADMC201. Power supplies should be decoupled at the power pins using a 0.1 F capacitor. A 220 nF capacitor must also be connected as close as possible between REFIN (Pin 33) and SGND (Pin 32). In addition, the IRQ requires a 15K pull-up to the VDD supply.
SYSTEM CLOCK FREQUENCY
The nominal range of the input clock for the ADMC201 is 6.25 MHz to 25 MHz. The external CLK frequency can be internally divided down by 2 by writing to Bit 5 of the SYSCTRL register. If the external CLK is faster than 12.5 MHz then it is necessary to internally divide it down.
DSP/CONTROLLER INTERFACE
The ADMC201 has a 12-bit bidirectional parallel port for interfacing with Analog Devices' ADSP-2100 DSP family or microcontrollers/microprocessors. The ADMC201 coprocessor is designed to be conveniently interfaced to the ADI's family of Fixed-Point DSPs. Figures 11 and 12 show the interfacing between the ADMC201 and the ADSP-2101/2105/2115, ADSP-2171, ADSP-2181, TMS320C2x DSPs. In the case of the TMS320C2x, some glue logic is required to decode the RD/WR lines and invert the CLKOUT1 signal. The ADSP-2101/2105/2115 CLKOUT frequency equals the crystal/clock frequency of its CLKIN. This signal (CLKOUT) can be used to directly drive the CLK line (Pin 21) on the ADMC201. The ADMC201 coprocessor can be operated with a clock frequency between the of 6.25 MHz and 25 MHz. If the clock frequencies is greater than 12.5 MHz, then it is necessary to internally divide down the external clock to derive the ADMC201's system clock (via SYSCTRL register).
ADDRESS BUS VDD A0-A13 ADDRESS DECODE EN CS IRQ RD WR CLK D0-D11* DATA BUS *NOTE: BY MAPPING THE ADMC201 DATA BUS TO THE TWELVE HIGHEST BITS OF THE ADSP DATA BUS, FULL-SCALE OUTPUTS FROM THE ADC CAN BE REPRESENTED BY 1.0 IN FIXED POINT ARITHMETIC. A0-A3
ADSP-2101/ DMS ADSP-2105/ ADSP-2115-20MHz IRQ2 ADSP-2171-10MHz RD ADSP-2181-10MHz
D0-D23 WR
ADMC201
CLKOUT
1. AN-407 2. AN-408 3. AN-409
AC Motor Control Experiments Using the ADMC200 Evaluation Board AC Motor Control Using the ADMC200 Motion Coprocessor Advanced Motor Control Techniques Using the ADMC200 Motion Coprocessor
-10-
Figure 11. ADI Digital Signal Processor/Microcomputer
REV. B
ADMC201
ADDRESS BUS VDD A0-A15 IS ADDRESS DECODE EN CS IRQ RD WR A0-A3
REGISTER ADDRESSING
TMS320C20 TMS320C25 TMS320C25-50
Four address lines (A0 through A3) are used in conjunction with the control lines (CS, WR, RD,) to select registers 0 through 15. The CS and RD control lines are active low. The registers are given symbolic names.
Table II.
INTn STRB R/W
ADMC201
Pin
CLKOUT1 D0-D15 CLK D0-D11
Function Enables the ADMC201 register interface (connect via chip select logic-active low) Places data from the internal register onto the data bus Loads the internal register with data on the data bus on its positive edge
CS RD WR
DATA BUS
Figure 12. TI Second Generation Devices TMS320C20/ C25/C25-50
In the case of the ADSP-2171/2181, the system clock is internally scaled, a 10 MHz system clock will derive a 20 MHz CLKOUT. In the case of the TMS320C2X, the CLKOUT1 signal is derived from the system clock divided by a factor of 4, consequently a 50 MHz TMS320C25-50 will derive a 12.5 MHz CLKOUT1 for use by the ADMC201. Note: a pull-up resistor is required on the IRQ (Pin 18) output from the ADMC201. The STOP (Pin 47) must be tied low if not in use.
DESCRIPTION OF THE REGISTERS
PHIP1/2/3 IX/IY
All unspecified register locations are reserved. SYSCTRL System Control Register (See Tables V, VI, VII). SYSSTAT System Status Register (See Table VII). ADCU These registers contain the results from ADCV the first three analog input channels ADCW U, V, and W. The output data format is twos complement and, therefore, Bit 0 is always zero as the A/D converter has 11-bit resolution. ADCAUX This register contains the conversion result of the auxiliary channels AUX0, AUX1, AUX2 or AUX3. PWMTM PWM Master Switching Period PWMCHA PWM Channel A On-Time PWMCHB PWM Channel B On-Time PWMCHC PWM Channel C On-Time PWMDT PWM Programmable Deadtime Value PWMPD PWM Programmable Pulse Deletion Value ID/IQ These are the results of the reverse rotation (torque and flux components). PHV1/2/3 These are the results from the forward Clarke Transformation.
VX, VY RHOP
RHO
PIODATA
PIOCTRL
The inputs for reverse vector transformation (Clarke and Park). These registers contain the results of the Clarke transformation that are the inputs to the reverse Park rotation. VX, VY contain the results of the forward Park rotation. RHOP is the angle used during the forward vector transformation. Writing to the RHOP register causes the forward rotation to start based on values in RHOP, VD and VQ registers. RHO is the angle used during the reverse vector transformation. Writing to this register starts the reverse rotation using the values in the RHO, PHIP1/2/3 registers. RHO and RHOP are unsigned ratios of 360. For example, 45 degrees would be 45/360 x 212. Write to this register to change the digital outputs and read from it to determine the state of digital inputs. This register is used to configure the digital I/O as input or output and to enable interrupt on change of state.
REV. B
-11-
ADMC201
Table III. Write Registers
Name RHO PHIP1/VD PHIP2/VQ PHIP3 RHOP PWMTM PWMCHA PWMCHB PWMCHC PWMDT PWMPD PIOCTRL PIODATA SYSCTRL
A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Register Function Load RHO () and Start Reverse Transform Reverse Rotation Direct Input/Forward Direct Input Reverse Rotation Direct Input/Forward Direct Input Reverse Rotation Direct Input Load RHOP () and Start Forward Transform PWM Master Switching Period PWM Channel A On-Time PWM Channel B On-Time PWM Channel C On-Time PWM Programmable Deadtime (7-Bit Register) PWM Pulse Deletion Value (7-Bit Register) Digital I/O Control Digital I/O Data Write (6-Bit Register) System Control Reserved Reserved
Table IV. Read Registers
Name ID/PHV1/VX IQ/PHV2 IX/PHV3 IY/VY ADCV ADCW ADCAUX ADCU
A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Register Function Reverse Rotation Result (IDS)/Forward Result Cos +0 Reverse Rotation Result (IQS)/Forward Cos +120 Reverse Clarke Cos +0/Forward Result Cos +240 Reverse Clarke Cos +90/Forward Cos +90 Reserved A/D Conversion Result Channel V A/D Conversion Result Channel W A/D Conversion Result Auxiliary Channel A/D Conversion Result Channel U Reserved Reserved Reserved Digital I/O Data Read (6-Bit Register) System Control System Status Reserved
PIODATA SYSCTRL SYSSTAT
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REV. B
ADMC201
Table V. System Control (SYSCTRL) Registers Table VII. SYSCTRL Analog Input Channel Selection
Bit 0 1 3 4 5 6 7 8 10
Function Auxiliary Channel Selection Auxiliary Channel Selection Enables U Channel Conversion (1 = Enable) Two-/Three-Phase Mode Enables AUX Channel Conversion (0 = Disable, 1 = Enable) Divide External Clock by 2 (0 = No, 1 = Yes) Park Interrupt Enable ADC Interrupt Enable (0 = Disable, 1 = Enable) IRQ Pin Format (Edge or Level Based Interrupt Requests) (0 = Edge) Reverse Rotation (0 = 2/3, 1 = 3/3) Forward Rotation (1 = Enable)
RESET Default 0 0 0 0 0 0 0 0 0
Bit 3 0 0 1 1
Bit 4 0 1 0 1
Channels Converted V, W (Default) V, W, AUX U, V, W U, V, W, AUX
Mode Two-/Three-Phase Two-/Three-Phase Three-/Three-Phase Three-/Three-Phase
Bit 0, 1 Auxiliary Channel Selection. Bit 3 Channel U Conversion Enable. If Bit 3 is set to 1, then Channel U will be converted along with V, W and/or AUX. This bit selects three-/three-phase mode. Aux Channel Conversion Enable. If Bit 4 is set to 1, then the AUX input will be converted along with the channels V, W and/or U. If Bit 5 = 1, then the external clock will be divided by two to derive the system clock. If the external clock frequency is greater than 12.5 MHz, then this bit must be set. Park Interrupt Enable. This bit allows interrupts to be generated when the Park rotation is completed. ADC Interrupt Enable. This bit allows interrupts to be generated when the analog-to-digital conversion process is complete. IRQ Pin Format--Edge or Level Interrupt Selection. If Bit 8 is set to 0, then an interrupt will cause a pulse of one system clock to be generated on the IRQ pin. If Bit 8 is set to 1, then an interrupt causes the IRQ output to go LOW (logic 0). The IRQ output pin will remain LOW until the SYSSTAT register is read. If Bit 10 is set to 1, then the reverse Park transformation will be formed in 3/3 mode. For Forward transformations, this bit must be set to 1.
Bit 4
Bit 5
Bit 6 Bit 7
Table VI. SYSCTRL Auxiliary Channel Selection
Bit 0 0 0 1 1
Bit 1 0 1 0 1
Auxiliary Channels Converted AUX0 AUX1 AUX2 AUX3 Bit 8
Bit 10
REV. B
-13-
ADMC201
Table VIII. System Status Register (SYSSTAT)1
Bit 0
Function A/D Conversion Completion Interrupt (1 = True) Vector Transformation Completion Interrupt (1 = True) Digital I/O Change of State Interrupt (1 = True) Rotation Results are Valid (1 = Valid) IRQ Generated from This Device (1 = True)
RESET Default
Table IX. Programmable Digital I/O Control Register (PIOCTRL)
Bit 0 0 1 0 0 X2 0 2 3 4 5 6 7 8 9 10 11
Function Programmable Digital I/O Direction Bit 0 (0 = Input, 1 = Output) Programmable Digital I/O Direction Bit 1 (0 = Input, 1 = Output) Programmable Digital I/O Direction Bit 2 (0 = Input, 1 = Output) Programmable Digital I/O Direction Bit 3 (0 = Input, 1 = Output) Programmable Digital I/O Direction Bit 4 (0 = Input, 1 = Output) Programmable Digital I/O Direction Bit 5 (0 = Input, 1 = Output) Programmable Digital I/O Bit 0 Interrupt (0 = Disable, 1 = Enable) Programmable Digital I/O Bit 1 Interrupt (0 = Disable, 1 = Enable) Programmable Digital I/O Bit 2 Interrupt (0 = Disable, 1 = Enable) Programmable Digital I/O Bit 3 Interrupt (0 = Disable, 1 = Enable) Programmable Digital I/O Bit 4 Interrupt (0 = Disable, 1 = Enable) Programmable Digital I/O Bit 5 Interrupt (0 = Disable, 1 = Enable)
RESET Default 0 0 0 0 0 0 0 0 0 0 0 0
1
2 4 11
NOTES 1 Reading this register clears the interrupt status flags Bits 0, 1, 2 and 11. 2 Undefined until the first Vector Transformation has started
Bit 0
A/D Conversion Completion Interrupt. This register is set to 1 when the A/D conversion process has completed and ADC interrupts have been enabled in the SYSCTRL register. Bit 1 Interrupt Status. This register is set to 1 when the Vector Transformation is completed and the Vector Transformation completion interrupts have been enabled. Bit 4 This bit is set to 1 when the rotation results are valid reading this. Bit 11 If any interrupt source on the ADMC201 occurs, then this bit is set to 1.
Bits 0-5
Sets corresponding Digital I/O bits as either input or output.
Bits 6-11 Configures Digital I/O Bits 0-5 as interrupt on change of state sources. Enabling interrupts for bits configured as output has no effect.
-14-
REV. B
ADMC201
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
68-Lead Plastic Leaded Chip Carrier (P-68A)
0.175 (4.45) 0.169 (4.29)
0.995 (25.27) SQ 0.985 (25.02)
9 10 PIN 1 IDENTIFIER 61 60
0.050 (1.27) TYP 0.925 (23.50) 0.895 (22.73)
PIN 1 IDENTIFIER
TOP VIEW
(PINS DOWN)
BOTTOM VIEW
(PINS UP)
0.019 (0.48) 0.017 (0.43) 0.029 (0.74) 0.027 (0.69)
26 27 44 43
0.954 (24.23) SQ 0.950 (24.13)
0.104 (2.64) TYP
REV. B
-15-
PRINTED IN U.S.A.
C2072a-1.5-4/00 (rev. B)

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